In some data communications systems which employ serial data links, the receiving station must not only receive the raw data, but it must also discern from the data the beginning and end of desired groupings of bits so that the data communicated thereby can be properly decoded. In one prior art system this is accomplished by use of a predetermined sequence of "flag" bits between packets (see for example U.S. Pat. Nos. 4,713,808 and 4,897,835). The flag bits can for example be, a 20-bit flag comprised of four "1"s, four "0"s, three "1"s, three "0"s, two "1"s, two "0"s, one "1," and one "0" ("11110000111000110010"). In such a system this flag is inserted between each pair of packets. When the receiver detects this sequence in the incoming data, it recognizes the sequence as a flag and treats the following bits as the beginning of a new packet. This process of segregating incoming data into desired groupings is commonly known as framing.
In one prior art system, the packets into which the data are organized are always 240 bits in length. Several of the packet's component fields are dedicated to protocol data, such as data indicating the time slot number in which the packet is transmitted and a format code indicating the type of data the packet contains. The remainder of the packet is available for transmitting message data. If a message is too long to send in one packet, rather than lengthening the packet, the system distributes the message data among several chained packets. The certainty of the packet length permits a received packet to be properly framed even if one of the two flags adjoining it is corrupted. This is accomplished by providing circuitry in the associated receiver that checks for both the leading and trailing flags surrounding a packet and considering the packet properly framed if either flag is detected.
The particular circuitry that can be used to implement this leading/trailing framer comprises a 281-bit shift register through which the serial data is clocked as it is received. A first flag detect circuit checks bits 1 through 20 each clock cycle to determine whether they match the known 20-bit flag pattern. A second flag detect circuit similarly checks bits 261 through 280. (Bit 281 is checked in an auxiliary flag detect circuit discussed more fully below). If either the first or second flag detect circuits detects the known flag sequence, the data in bits 21 through 260 are considered to comprise a properly framed 240-bit packet. These 240 bits are then latched into a memory circuit and processed, while newly received serial data continues to be introduced into the shift register for framing of the next packet.
It will be recognized that a happenstance occurrence of the flag sequence bits embedded in the packet data results in an improperly framed packet. To minimize this problem, it is desirable to use relatively long flag sequences, since each additional bit halves the likelihood of this type of framing error. However, as the flag sequences are lengthened, the likelihood that the flags themselves may be corrupted during transmission also increases. If two consecutive flag sequences are corrupted, then even the leading/trailing framing technique described above will fail in framing the packet therebetween.
From the foregoing, it will be recognized that framing techniques are subject to two principal sources of error: corruption of true flag sequences (preventing framing), and embedded false flag sequences (causing improper framing). It is an object of the present invention to provide an improved packet framing system in which the effects of these error mechanisms can be minimized.
In accordance with the present invention, this object is achieved by anticipating particular variable data bits that will be found in a desired grouping of data, and framing the desired group of data in the received signal by detecting the anticipated data bits in predetermined bit positions.
The foregoing and additional objects, features and advantages of the invention will be more readily apparent from the following detailed description thereof, which proceeds with reference to the accompanying drawings.